Current database storage computing systems achieve zero-loss high availability by replicating state changes from the primary server to its high-availability target server. Generally, a journal or write log is recorded which includes a record of the most recent updates to the database or write commands executed to the storage. In order to have zero-loss of data upon a primary server failure, a procedure known as synchronous replication can be performed.
When performing storage replication, many database systems utilize remote direct memory access (RDMA). RDMA permits low-latency networking between remote computer systems when accessing direct memory from one computer system into another without accessing the operating system of the remote computer system being targeted. RDMA can be used over InfiniBand (TB) or Ethernet.
Although this type of memory access is often used due to its adequacies when recording updates to slower storage systems, e.g. flash memory, it can create a major computing “bottleneck” with respect to the performance of in-memory applications which utilize high-speed non-volatile memory (NVRAM). For instance, one major characteristic of NVRAM is the fact that this type of memory is significantly faster than flash memory when executing both reading and writing commands and requires less computing power.
Another way, as known in the art, for executing high speed replication between remote computer systems is to incorporate non-transparent bridging (NTB) on a peripheral component interconnect express (PCIe) connection between the two computer systems. This type of configuration can allow the primary system to “see” the physical address space of the high-availability partner and use store instructions targeted at the appropriate physical addresses in the partner in order to replicate the NVRAM. However, there are many disadvantages of this type of setup.
First, network security issues arise and the inability to safeguard the provider or target system from virus or other bugs in the application that cause the system to write to inappropriate memory addresses in the partner, causing serious and costly system failures or system corruption with the memory. Furthermore, when there are two applications running on the primary system, which is highly likely, the replication process will not work because the memory would need to be separately replicated to different, non-contiguous areas of physical memory on the partner which poses another costly and impractical attempt to replicate using this configuration.
Second, the performance of the processors can be significantly affected. As will be understood for current processors, when a stored instruction is executed on memory accessed via the PCIe interconnect, the data is broken up into packets that only contain 16 bytes each. This is much smaller than the maximum payload size of up to 4096 bytes even if the widest possible stored instruction is used (which stores 32 bytes). Breaking the data into these packets during transfer unfortunately produces extremely poor use of the PCIe bandwidth and actually increases latency.
In view of the foregoing, there is a need for improved memory replication and memory modification among networked computer systems at low latency.